New hardware security threats occur in emerging three-dimensional (3D) integrated circuits (ICs). It is imperative to study the potential countermeasures for 3D ICs.
Relevant publications:
- Dofe J, Yan C, Kontak S, Salman E, Yu Q. Transistor-level camouflaged logic locking method for monolithic 3D IC security, in 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST). ; 2016 :1-6.
- Dofe J, Yu Q, Wang H, Salman E. Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs, in Proceedings of the 26th Edition on Great Lakes Symposium on VLSI. New York, NY, USA: ACM ; 2016 :69–74.
- Dofe J, Gu P, Stow D, Yu Q, Kursun E, Xie Y. Security Threats and Countermeasures in Three-Dimensional Integrated Circuits, in Proceedings of the on Great Lakes Symposium on VLSI 2017. New York, NY, USA: ACM ; 2017 :321–326.
- Yan C, Dofe J, Kontak S, Yu Q, Salman E. Hardware-Efficient Logic Camouflaging for Monolithic 3D ICs . IEEE Transactions on Circuits and Systems II: Express Briefs. 2018;65 (6) :799 - 803.
- Dofe J, Yu Q. Exploiting PDN Noise to Thwart Correlation Power Analysis Attacks in 3D ICs, in Proceedings of the 20th System Level Interconnect Prediction Workshop. New York, NY, USA: ACM ; 2018 :6:1–6:6.